A central processing unit (CPU) or processor is the hardware within a computer system which executes the instructions of a computer program by performing the basic arithmetic, logical and input and output operations of the computer system. Cache memory components of a processor are data storage structures that are used by the processor to reduce the average time that it takes to access memory. It is cache that stores copies of data that are located in the most frequently used main memory locations. Cache memory is memory that is smaller in storage capacity than main memory but is memory that can be accessed much more quickly.
Some processors with cache memory support load speculation. Processors that support load speculation employ load speculation to reduce processor-memory exchanging bottlenecks or latency by putting data into cache in advance of executing an actual load instruction that corresponds to the data. Load speculation involves predicting the loads that need to be prospectively executed. As a part of this process, mispredictions can occur. Mispredictions are predictions that incorrectly identify the loads that need to be prospectively executed. These loads are called speculative bad loads. Mispredictions can result in the initiation of the execution of such loads.
When it is determined that a misprediction or some other action that results in the occupation of the load queue by speculative bad loads has occurred, a flush of the load queue is necessary to free the load queue for incoming loads. The flushing of the speculative bad loads from the load queue results in their cancellation. When a load queue flush is signaled, speculative bad loads can be executing at stages of the instruction pipeline that are both internal and external to the processor. Accordingly, a flush of the load queue can involve speculative bad loads executing in the instruction pipeline at stages both internal and external to the processor.
In a computer system, a device interconnect structure is generally utilized that connects a processor to other devices or processors. The interconnect structure is called a bus or interconnect fabric. In some conventional systems the interconnect fabric does not enable loads that are executing at places therein to be cancelled. As such, a flush of the load queue that involves speculative bad loads executing at places in the interconnect fabric can be prevented until the speculative bad loads are returned to the load queue. Accordingly, new loads, which must be placed into the load queue before being executed, can be prevented from accessing the cache system of a processor for several cycles until the speculative bad loads are returned from the interconnect fabric to the load queue for cancellation purposes. As such, some conventional approaches feature an inefficient instruction pipeline flush handling scheme that results in unsatisfactory delays in the execution of important load queue flushes.